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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appear in this document. contact generalplus technology inc. to obtain the latest version of devi ce specifications before plac ing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. g g p p l l b b 3 3 0 0 b b 640 dots lcd controller with 48kb rom apr. 16, 2009 version 1.1 in addition, generalplus products are not authorized for use as critical components in life support devices/ systems or aviatio n devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the expre ss written approval of generalplus.
gplb30b ? generalplus technology inc. proprietary & confidential 2 apr. 16, 2009 version: 1.1 table of contents page 1. general description .......................................................................................................................................................................... 3 2. block diagram ...................................................................................................................................................................................... 3 3. features .................................................................................................................................................................................................. 3 4. appication field .................................................................................................................................................................................... 4 5. signal descriptions ............................................................................................................................................................................ 4 5.1. pad a ssignment ................................................................................................................................................................................. 5 6. functional descriptions.................................................................................................................................................................. 6 6.1. m emories ............................................................................................................................................................................................ 6 6.2. m ap of m emory and i/o s .................................................................................................................................................................... 6 6.3. o perating s tates ............................................................................................................................................................................... 6 6.3.1. operating mode ........................................................................................................................................................................ 6 6.3.2. standby mode ........................................................................................................................................................................... 6 6.3.3. halt mode .................................................................................................................................................................................. 6 6.4. lcd c ontroller /d river .................................................................................................................................................................... 7 6.5. lcd v oltage g enerator ................................................................................................................................................................... 7 6.6. l ow v oltage r eset ............................................................................................................................................................................ 7 6.7. w atchdog t imer (wdt) ..................................................................................................................................................................... 7 6.8. m ask o ptions ...................................................................................................................................................................................... 7 6.8.1. 32768 oscillator ......................................................................................................................................................................... 7 6.8.2. watchdog timer ......................................................................................................................................................................... 7 6.8.3. pc[0:7]/seg[39:32] .................................................................................................................................................................. 7 6.8.4. rosc32k select .......................................................................................................................................................................... 7 6.8.5. system r osc select ................................................................................................................................................................... 7 6.8.6. low voltage reset ...................................................................................................................................................................... 7 7. electrical specifications ............................................................................................................................................................... 8 7.1. a bsolute m aximum r atings ............................................................................................................................................................... 8 7.2. dc c haracteristics ........................................................................................................................................................................... 8 7.3. t he r elationships between the f osc and the r osc ........................................................................................................................... 9 7.4. t he r elationships between the f osc and the vdd .......................................................................................................................... 9 7.5. t he r elationships between the f osc32k and the rosc32k .................................................................................................................... 9 7.6. t he r elationships between the f osc32k and the vdd ...................................................................................................................... 9 8. application circuits ......................................................................................................................................................................... 10 8.1. 512 d ots lcd d river , 32 s egments 16 c ommons , 1/5 b ias , 56 k eys + o n /o ff k ey , i nternal rosc - (1) ................................ 10 8.2. 640 d ots lcd d river , 40 s egments 16 c ommons , 1/5 b ias , 96 k eys , xtal + e xternal rosc - (2) ..........................................11 9. package/pad locations ................................................................................................................................................................... 12 9.1. o rdering i nformation ..................................................................................................................................................................... 12 10. disclaimer ............................................................................................................................................................................................. 13 11. revision history ................................................................................................................................................................................. 14
gplb30b ? generalplus technology inc. proprietary & confidential 3 apr. 16, 2009 version: 1.1 lcd controller 1. general description the gplb30b, an 8-bit cmos mi croprocessor, contains 2240 bytes working ram, 48k bytes rom, 16 i/os, interrupt/wakeup controller, and automatic display controller/driver for lcd. furthermore, a sleep (power-down) function is also built in to extend power life. the gplb30b is designed with state-of-the-art technology to fulfill lcd application needs, especially for hand-held products. 2. block diagram rc-oscillator system clock gen. power supply voltage detect 48k bytes rom 2240 bytes ram one 16-bit / auto-reload timer 32 khz oscillator & time base 8-bit micro-processor max.16 i/o ports 16 commons x 40 segments lcd driver 32khz rosc (i/o) com[15:0] seg[39:0] lcd ram 80 bytes 32khz pa[7:0] pc[7:0] 8 8 note1: pc[0:7] share pins with seg[39:32] (mask option). 3. features ? built in 8-bit processor 2240 bytes sram 48k bytes rom max. operating speed: 5.0mhz @ 2.2v - 5.5v cpu clock is software programmable, can be /1, /2, /4, /8, /16, /32, /64 r-oscillator clock frequency provides 4 wake-up sources provides 4 interrupt sources ? programmable lcd driver up to 40 segments, up to 16 commons, maximum 640 dots 1/3, 1/4, 1/5 bias; 1/4, 1/8, 1/16 duty capability 80 bytes dedicated lcd ram built-in voltage regulator to generate vlcd for lcd driver 27-level contrast control (2.98v - 5.75v) ? power saving sleep mode ? low voltage reset 2.1v low voltage reset ? peripherals max. 16 i/o pins (pa[7:0], pc[7:0]) . dedicated i/os: pa[0:7], . shared pin i/os: pc[0:7]/seg[39:32] built-in system rc-oscillator built-in rc 4mhz or built-in c external r decided by mask option built-in 32.768khz oscillator for real time clock function xtal or built-in rc oscillato r or built-in c external 3m ? r oscillator decided by mask option one 16-bit reloadable timer/counters watchdog timer for reliable operation ? low power consumption: 650 a typical @ 3.0v, f cpu = 1.0mhz, f osc = 4.0mhz 25 a typical halt current @ 3.0v <1 a typical standby current @ 3.0v ? wide operating voltage range: 2.2v - 5.5v
gplb30b ? generalplus technology inc. proprietary & confidential 4 apr. 16, 2009 version: 1.1 4. appication field ? scientific calculator ? data bank 5. signal descriptions total: 75 pins mnemonic pin no. type description seg31 - 0 seg39 - 32 / pc0 - 7 59-28, 4-11 o i/o lcd driver segment output. seg39 - 32 optioned to pc0 - 7. com15 - 0 27-12 o lcd driver common output. pa7 - 0 3-1, 75-71 i/o port a is a bi-directional i/o port, which can be software programmed as wake up i/o. rosc 69 i r-oscillator input, connect to vdd through a resistor. resetb 68 i system reset input, low active. x32i 67 i 32.768khz crystal input or connect to vdd through a resistor (option). x32o 66 o 32.768khz crystal output. test 64 i test input. cup1, cup2 63, 62 p lcd voltage generator. charge pump capacitor inter-connection pins v2x 61 p lcd voltage generator for vdd*2. vlcd 60 p lcd voltage generator. vdd 70 p power supply voltage input. vss 65 p ground reference. legend: i = input, o = output, p = power
gplb30b ? generalplus technology inc. proprietary & confidential 5 apr. 16, 2009 version: 1.1 5.1. pad assignment
gplb30b ? generalplus technology inc. proprietary & confidential 6 apr. 16, 2009 version: 1.1 6. functional descriptions 6.1. memories the gplb30b contains 48k-byte rom and 2240-byte sram. 6.2. map of memory and i/os *int source: - ext int - tbl (2/4/8/16hz) - tbh (128/256/512/1khz) - timer0 rom (bank)h i/o & $0000-$003f $3e00-$3eff $4000-$7fff $8000-$bfff $c000-$fff9 $fffa-$ffff cpu view $04000-$07fff $08000-$0bfff 0h 1h rom view bank address: $0 $c000-$ffff always mapping into 0l 0 1 2 0l reg. $0040-$08ff rom (bank)l interrupt rom dpram ram 0l 1l $0c000-$0ffff 1. user?s program should start from $c000. $8000-$87ff in bank0 is the test program area. 2. user?s program interrupt vector: $fffa ~ $ffff. 3. test program interrupt vector: $fff2 ~ $fff7. 6.3. operating states there are three operation modes in gplb30b: standby, halt and operating. the following table shows the differences between these modes. operating halt standby cpu on off off 32768hz oscillator on on off lcd driver on on/off off 6.3.1. operating mode in operating state, all functions (cpu, 32768hz oscillator, timer/counter, lcd driver?) are ac tivated. generally speaking, this mode consumes the highest power. 6.3.2. standby mode turn off cpu and 32768hz oscillator to activate standby mode. the standby mode is a mode that the device is placed in its lowest current consumption state. in standby mode, all functions are turned off; in addition, ram and i/os will remain in their previous states. 6.3.3. halt mode entering halt mode turns off cpu but still keeps 32768hz oscillator running. in halt mode, cpu clock halts and waits for an event (key press, timer overflow) to wake up. the 32768hz related functions, such as timer/counter and lcd driver, may remain active in the halt mode.
gplb30b ? generalplus technology inc. proprietary & confidential 7 apr. 16, 2009 version: 1.1 the following figure is the gplb30b state diagram: halt operating standby cpu off, 32768 oscillator off wake-up or user reset c p u o f f , 3 2 7 6 8 o s c i l l a t o r o n w a k e - u p o r u s e r r e s e t gplb30b state diagram g. the lcd driver in gplb30b upports 1/16 duty and 1/5 bias. d. the vlcd is adjustable from 2.98v to 5.75v ith 27 levels. etector will generate a system reset if power supply voltage 6.4. lcd controller/driver the gplb30b contains a 640-dot lcd controller/driver. programmer is able to define the lcd configuration by setting the lcd control register. once the lcd configuration is completed, the desired pattern can be displayed by filling the lcd buffer with proper data. the lcd driver can also operate during sleep by keeping 32768hz oscillator runnin s 6.5. lcd voltage generator the gplb30b offers a voltage regulator and a charge-pumping circuit. the voltage regulator supplies the charge-pumping circuit a reference voltage to generate vlcd. users can get the desired vlcd by changing the output reference voltage (writing to register) of the voltage regulator. enabling the voltage regulator and charge-pumping circuit gets a stable vlcd that will not be affected by vd w 6.6. low voltage reset the gplb30b provides a low voltage reset function. the voltage drops below 2.1v. d 6.7. watchdog timer (wdt) an on-chip watchdog timer is also available in the gplb30b. the wdt is designed to recover the system from abnormal operation. in some cases, if wdt is not cleared for one second, the wdt will generate a system reset to restart system. if wdt is enabled, the wdt should be cleared through software programming every 0.5 seconds to avoid accidental reset. note that the wdt only works when 32768hz clock is activated. 6.8. mask options 6.8.1. 32768 oscillator x?tal32k rosc32k 6.8.2. watchdog timer enable disable 6.8.3. pc[0:7]/seg[39:32] each port/segment can be optioned as i/o or lcd segment individually. 6.8.4. rosc32k select 1). built in rc 2). built in c external r 6.8.5. system r osc select 1). built in rc 2). built in c external r 6.8.6. low voltage reset 1). disable 2). enable
gplb30b ? generalplus technology inc. proprietary & confidential 8 apr. 16, 2009 version: 1.1 7. electrical specifications 7.1. absolute maximum ratings characteristics symbol ratings dc supply voltage v + < 7.0v input voltage range v in -0.5v to v + + 0.5v operating temperature t a 0 to +60 storage temperature t sto -50 to +150 note: stresses beyond those given in the absolute maximum rating ta ble may cause operational errors or damage to the device. for no rmal operational conditions, see ac/dc elec trical characteristics. 7.2. dc characteristics limit characteristics symbol min. typ. max. unit test condition operating voltage vdd 2.2 - 5.5 v operating current i op - 650 - a vdd = 3.0v, f cpu = 1.0mhz, f osc = 4.0mhz, no load halt current i halt1 - 25 - a vdd = 3.0v, 32k x?tal on, maximum vlcd, strobe on, no lcd panel standby current i stby - - 1.0 a vdd = 3.0v, all off input high level v ih 2.0 - - v vdd = 3.0v input low level v il - - 0.8 v vdd = 3.0v output high current (i/o) i oh -1.0 - - ma vdd = 3.0v, v oh = 2.4v output sink current (i/o) i ol 1.0 - - ma vdd = 3.0v, v ol = 0.8v lcd driver voltage (v lcd - vss) v lcd 2.98 - 5.75 v vdd = 3.0v, 1/5 bias, no load osc resistor r osc - 75k - f osc = 4.0mhz @ 3.0v system oscillator frequency f osc -10% 4.1 +10% mhz built-in c external 75k resistor oscillator or built-in rc 4mhz oscillator @ 3.0v - 32.768 - xtal32k -10% 34 +10% built-in c external 3m resistor oscillator 32k oscillator frequency f32k -30% 36 +30% khz built-in rc oscillator@ 3.0v note1: v lcd should be higher than vdd to prevent forward biasing the p-n junction of i/o output pmos. note2: if not mentioned specially, the te st condition is 2.2v~5.5v@25
gplb30b ? generalplus technology inc. proprietary & confidential 9 apr. 16, 2009 version: 1.1 7.3. the relationships between the f osc and the r osc 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 40 60 80 100 120 140 160 180 200 220 240 rosc(kohms) fosc(mhz) vdd=3v 7.4. the relationships between the f osc and the vdd 3.8 3.9 4 4.1 4.2 4.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(volts) fosc(mhz) fosc(builtin rc) fosc(builtin c ext 75k r) 7.5. the relationships between the f osc32k and the r osc32k 20 25 30 35 40 45 50 55 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 rosc32k(mohms) fosc32k(khz) vdd=3v 7.6. the relationships between the f osc32k and the vdd 30 31 32 33 34 35 36 37 38 39 40 41 42 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(volts) fosc32k(khz) fosc32k(builtin rc) fosc32k(builtin c ext 3mohm r)
gplb30b ? generalplus technology inc. proprietary & confidential 10 apr. 16, 2009 version: 1.1 8. application circuits 8.1. 512 dots lcd driver, 32 segments 16 commons, 1/5 bias, 56 keys + on/off key, internal rosc - (1) gplb30b lcd panel (16x32) pc0 pc1 pc6 pc2 pc7 pa1 pa2 pa3 pa4 pa5 ..... ..... ..... ..... ..... resetb v2x cup2 cup1 pa0 pa1 pa2 pa3 pa4 pa5 vlcd pc[7:0] com[15:0] seg[31:0] ..... pa6 ..... pa6 pa7 ..... pa7 vdd 200uf 0.1 uf 0.1 uf 1 uf 0.1 uf 0.1 uf * using segments for lcd display only; system rosc select bui lt in rc rosc4m; 32k oscillator select built in rc rosc32k.
gplb30b ? generalplus technology inc. proprietary & confidential 11 apr. 16, 2009 version: 1.1 8.2. 640 dots lcd driver, 40 segments 16 commons, 1/5 bias, 96 keys, xtal + external rosc - (2) gplb30b lcd panel (16x40) seg0 seg1 seg14 seg2 seg15 pa0 pa1 pa2 pa3 pa4 ..... ..... ..... ..... ..... rosc x32i x32o resetb pa0 pa1 pa2 pa3 pa4 com[15:0] seg[51:0] ..... pa5 pa5 ..... vdd 30p v2x cup2 cup1 vlcd 0.1 uf 1 uf 0.1 uf 75 k 0.1 uf c2* c3* 20p 20p vdd 200 uf 0.1 uf c1 r1 * using segments for both lcd display and key scan; system rosc se lect built in c external 75k rosc; 32k oscillator select xtal . note1: c2/c3 values in above application circuit are for design guidance only. different capacitor values may be required for differe nt crystal used. usually, the values of c2/c3 are in the range 12~20pf. note2: to avoid the noise interference on pcb around r-oscillator and crystal circuit, following rules are recommended: 1). r1 and c1 should be placed as close as possible to rosc pin. 2). c2, c3 and crystal should be placed as close as possible to x32i and x32o. a shielding by ground is suggested.
gplb30b ? generalplus technology inc. proprietary & confidential 12 apr. 16, 2009 version: 1.1 9. package/pad locations 9.1. ordering information product number package type GPLB30B-NNNV-C chip form note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z).
gplb30b ? generalplus technology inc. proprietary & confidential 13 apr. 16, 2009 version: 1.1 10. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. generalplus makes no warranty, express, st atutory implied or by description regarding the information in th is publication or regarding the freedom of the described chip(s) from patent infringement. further, generalplus makes no warranty of merchantability or fitness for any purpose. generalplus reserves the right to halt production or alter the specifications and prices at any time without notice. acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are curr ent before placing orders. products descri bed herein are intended for use in normal com mercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by generalplus for such applications. please note tha t application circuits illustrated in this document are for reference purposes only.
gplb30b ? generalplus technology inc. proprietary & confidential 14 apr. 16, 2009 version: 1.1 11. revision history date revision # description page apr. 16, 2009 1.1 1. add relationship waveform for frequency at section 7.3, 7.4, 7.5, 7.6 2. modified application circ uit in section 8.1 & 8.2 9 10,11 mar. 6, 2009 1.0 1.modified rom size from 50k to 48k 2.modified max operating speed 3.modified low power consumption; 4.modified dc characteristics 3,6 3 3 8 oct. 23, 2008 0.1 preliminary data sheet 10

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